Constraint failure with rand_mode(0)

SystemVerilog
, ,
1

Following code is showing constraint failure.
Is it expected as per LRM?

module top;
        class c;
                rand int a,b;

                constraint cc { a < b;}
        endclass

        c ch;

        initial begin
                ch = new();
                ch.a = 5;
                ch.b = 1;
                ch.a.rand_mode(0);
                ch.b.rand_mode(0);

                ch.randomize();
        end
endmodule

Thank you

2

The constraint failure is coming because the value of a is less than b, even if you set the rand_mode to 0, the constraints are still evaluated when you call randomize() function.

3

In reply to sharat:

Hi Sharat,
Thanks for your reply.
But, is there any LRM reference to confirm it.

4

In reply to ravi:

Hi Ravi,

Sorry, I don’t have a LRM Reference.

5

In reply to ravi:

you need to disable the constraint as well using constraint_mode. I couldn’t find any specific LRM section for this rule, but following section makes this clear:

Section 18.11.1:
Normally, calling the randomize method of a class that has no random variables causes the method to behave as a checker. In other words, it assigns no random values and only returns a status: 1 if all constraints are satisfied and 0 otherwise.

6

In reply to sharat:

18.8 Disabling random variables with rand_mode()
The rand_mode() method can be used to control whether a random variable is active or inactive. When a random variable is inactive, it is treated the same as if it had not been declared rand or randc. Inactive variables are not randomized by the randomize() method, and their values are treated as state variables by the solver. All random variables are initially active.

According to 18.3 Concepts and usage, constraint expressions must be satisfied(evaluate true), otherwise the call to randomize fails.