Constraint existence of value into an array

SystemVerilog
, , , ,
4

In reply to nimrodw:

You cannot have expressions containing unpacked arrays unless you use a foreach loop or a reduction method.

class some_object extends uvm_object;
  rand bit [1:0] arr[6];
  constraint the_constraint_c{
    arr.sum() with {int'(item==1)) == 1;
    arr.sum() with {int'(item==2)) == 1;
    arr.sum() with {int'(item==3)) == 1;
  }
 
function new(string name = "some_object");
  super.new(name);
endfunction
endclass: some_object

I am constraining the sum of the number of times each elements equals 1,2, or 3 to be 1.