Consequence of not to be an "assignment-like context"

SystemVerilog
,
1

In the LRM, it is stated that these example should not be considered as an assignment-like context:

  • a static cast
  • a default correspondence between an expression in an assignment pattern and a field or element in a data object or data value

What is the consequence of this statement?

Especially, what is the difference between the default correspondence (as a non-assignment-like context) and
the nondefault correspondence (as an assignment-like context)?

Thanks a lot
Thomas

2

In reply to Thomas Kruse:

This refers the the default clause in an assignment pattern. Let’s say you had a struct with three elements

module top;
  typedef struct {bit [3:0] a; bit [7:0] b; bit [15:0] c;} ab_t;
  ab_t ab;
  initial begin
    ab = '{a: ~1'b0, default:~1'b0};
    $displayh("%p",ab); // # 
  end
endmodule

Normally each elements gets assigned in the context of the assignment to an individual field type. For field expression a:~1’b0, the operand 1’b0 gets extended before applying the operator, so the result is 4’b1111. But the default applies to fields ‘b’ and ‘c’ of different type. The expression ~1’b0 gets evaluated in a 1-bit context, becoming 1’b1, and afterwards gets 0-extended to the size of fields b and c.

I believe the part about a static cast not be considered as being part of an assignment-like context is a mistake in the LRM. I filed an errata.

3

In reply to dave_59:

Thanks a lot, Dave!

Your explanation is very helpful!

Best regards,
Thomas

4

In reply to dave_59:

BTW, I’ve tried this with several tools. Interestingly, all (!) tools have implemented the default clause as an assignment-like context. I’ve tried it with ~1’b0 and '1 as examples.