Connectivity of signal in different modes

SystemVerilog
, ,
1

Hello SVA Experts,

Have a Truth Table and require a connectivity check in different modes.
Signal Name - p_reset.
Mode-1, Value is 1.
Mode-2, Value is dynamic (src value = dst value)
Mode-3, Value is dynamic (src value = dst value)
Mode-4, No Check to be performed.

How does the assertion get framed in these different modes? Clk for assertion can be assumed to be 1uS.
Thanks,
Ravi

2

In reply to verif4ravi:

See section 16.12.16 Case in the IEEE 1800-2017 SystemVerilog LRM.

3

In reply to dave_59:

Thanks Dave,
These modes are like Functional(default), Scan and other power modes that the chip supports.
So I tried breaking the checks.

assert_prop : assert property (@(posedge clk) disable iff (rst) 
   (p_reset))
   else
    `uvm_error("p_reset went LOW ");

ap_connectivity_SRC_DST_p_reset: 
assert property(p_src_matches_dst(.source(`SRC.<signal1>),.dest(`DST.p_reset)));

Do they make sense or can still be optimized?