Connecting two modules using an interface

SystemVerilog
,
1

hello. i am new learner of system verilog. right now am trying to connect two modules using an interface. is it necessary to connect two modules via a top module when using interface…??? is there a way to connect directly from one module to another using interface…? like in verilog we simply instantiate second module from first module…??

following is the code which i wrote…

interface datamem;
logic [2:0] count;
logic [7:0] inst_out;
endinterface

module IF_Inter( input  logic rst,clk,inst_en,
	         datamem data);
always_ff @(posedge clk or posedge rst) begin
if (rst)
begin
data.count <= 3'b000;
end
else if(inst_en)
data.count <= data.count + 3'b001;
end
inst_mem_inter U_inst_mem_inter( .mem(data));
endmodule


module inst_mem_inter(datamem mem);
always_comb begin
case (mem.count) 
3'b000: mem.inst_out<=8'b00000000;
3'b001: mem.inst_out<=8'b00000101;
3'b010: mem.inst_out<=8'b01001010;
3'b011: mem.inst_out<=8'b01001111;
3'b100: mem.inst_out<=8'b10010000;
3'b101: mem.inst_out<=8'b10010101;
3'b110: mem.inst_out<=8'b11011010;
3'b111: mem.inst_out<=8'b11011111;
endcase
end
endmodule

this is not working and throwing an error because i have not instantiated the interface as we do in a top module. i am able to do it using top module and instantiating it. just want to know whether we can do directly or not ?

2

The problem is not with the connection between the two modules, but the fact the you have an interface port left unconnected. SystemVerilog requires that all interface ports be connected to actual interface instances. The reason for this is that interface ports are just hierarchical references to an interface instance. Although an interface may look like a struct data type, it is actually closer to a module in that it can have processes like initial/always blocks, continuous assignments, and other interface instance. These processes and variable declarations are allocated when the interface gets instantiated.

In your example, both modules could have referenced
count and
inst_out and would be referring to the same variable in the interface instance that needs to be connected to
IF_Inter

Simulation tools must enforce this rule because they need a place to allocate the variable and schedule any of the processes associated with the interface.

Synthesis tools do not always enforce this rule at the top level module because they are assuming some other step has taken care of implementing the hierarchy above the what is currently being synthesized.

3

In reply to dave_59:

Very well explained sir (Dave Rich). Understood the concept behind it. Thank You