The problem is not with the connection between the two modules, but the fact the you have an interface port left unconnected. SystemVerilog requires that all interface ports be connected to actual interface instances. The reason for this is that interface ports are just hierarchical references to an interface instance. Although an interface may look like a struct data type, it is actually closer to a module in that it can have processes like initial/always blocks, continuous assignments, and other interface instance. These processes and variable declarations are allocated when the interface gets instantiated.
In your example, both modules could have referenced
count and
inst_out and would be referring to the same variable in the interface instance that needs to be connected to
IF_Inter
Simulation tools must enforce this rule because they need a place to allocate the variable and schedule any of the processes associated with the interface.
Synthesis tools do not always enforce this rule at the top level module because they are assuming some other step has taken care of implementing the hierarchy above the what is currently being synthesized.