Conflict of initial blocks

SystemVerilog
,
1

I am using the code as follows,

module test(*);
initial begin
signal_1 = 0;
signal_2 = 0;
…
end
// logic ///
…
`ifndef DATA
initial begin
signal_1 =100;
signal_2 = 100;
end

2

In reply to Sanjeeva Dinesh:

Based on SystemVerilog scheduling semantics, signal_1 can be 0 or 100 which depends on the order of executing.

3

In reply to javatea:

Thank you for the reply
In my case, it takes 2nd value, i.e which is lastly updated

4

In reply to Sanjeeva Dinesh:

The code which you mentioned is not good, as it may create a race condition.
Instead, I think below will be good,

initial begin
  `ifndef DATA
     signal_1 = 100;
     signal_2 = 100;
   `else
     signal_1 = 0;
     signal_2 = 0;
    `endif
 end

If you have a situation where you need to do this in 2 separate initial block,
then please add `ifdef for the first initial block also, so that you make sure always one is executed.

`ifdef DATA
   initial begin
     signal_1 = 0;
     signal_2 = 0;
   end
`endif
`ifndef DATA
   initial begin
     signal_1 = 100;
     signal_2 = 100;
   end
`endif

Thanks,
Abhi

5

In reply to Sanjeeva Dinesh:
Verilog does not guarantee the execution order of initial and always blocks. Because of optimizations that a tool performs, it might pick one ordering one time and another ordering in a later version of the same tool.