Conflict of initial blocks

SystemVerilog
,
4

In reply to Sanjeeva Dinesh:

The code which you mentioned is not good, as it may create a race condition.
Instead, I think below will be good,

initial begin
  `ifndef DATA
     signal_1 = 100;
     signal_2 = 100;
   `else
     signal_1 = 0;
     signal_2 = 0;
    `endif
 end

If you have a situation where you need to do this in 2 separate initial block,
then please add `ifdef for the first initial block also, so that you make sure always one is executed.

`ifdef DATA
   initial begin
     signal_1 = 0;
     signal_2 = 0;
   end
`endif
`ifndef DATA
   initial begin
     signal_1 = 100;
     signal_2 = 100;
   end
`endif

Thanks,
Abhi