In reply to run2prem:
This is not polymorphism. Polymorphism is the same code behaving differently under different circumstances. SystemVerilog has compile time, or static polymorphism when you parameterize a module or class. Run-Time or dynamic polymorphism is implemented with virtual methods.
What you have done is override the add function in the Derived class. This “hides” the original add function.
You may want to read: Parameterized Classes, Static Members and the Factory Macros - Verification Horizons