Compile-time Polymorphism in SV

SystemVerilog
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3

In reply to dave_59:

Hi Dave,

You must call it with 3 arguments
Yes got it and agreed.

But within the ‘Derived’ class scope, we get two ‘add’ methods with different signatures. Yes, of course user has to resolve the call himself by specifying this. or super.

My query is

  1. This is a case of polymorphism or not?

  2. If so, is this function overloading or overriding?

I’m not sure how C++ or other OOP language handles this.

Thanks,
Prem