Compilation Error:: virtual interface XMR connected to task/function ref-port is not yet supported

Coverage
,
1

Hi ,

I wanted to have 15 instances of Covergroups.
I coded like this //


//__________COVERGROUP---------------//
covergroup cg_rate(ref bit[1:0] Rate)
cp_rate:Rate {
         bins GEN1={0};
         bins GEN2 ={1};
         bins GEN3 = {3};
endgroup
///------COVERAGE CLASS--------//
class cov_c extends ovm_component
virtual cov_if cov_if_inst;
cg_rate cg_rate_inst[15:0];

function void build_phase
for(int i=0;i<15;i++)
begin
cg_rate_inst[ i]=new(cov_if_inst.rate[0]);
end  
endfunction

endclass

//--------------COVERGAE INTERFACE-------//
interface cov_if
bit [1:0] rate[15;0];

assign rate[0]=top.rtl.rate[1:0];
assign rate[1]=top.rtl.rate[3:2];
....
endinterface

I am getting a Compilation error
*Error-[NYI] Not Yet Implemented
cov_c.sv, 358
Feature is not yet supported: Select of an interface array accessed through
virtual interface XMR connected to task/function ref-port is not yet
supported
*

How can i overcome this.
I modified the interface as

interface cov_if
bit [1:0] rate_0;
bit [1:0] rate_1;

assign rate_0=top.rtl.rate[1:0];
assign rate_1=top.rtl.rate[3:2];
....
endinterface
class cov_c extends ovm_component
virtual cov_if cov_if_inst;
cg_rate cg_rate_inst[15:0];

function void build_phase

cg_rate_inst[0]=new(cov_if_inst.rate_0);
cg_rate_inst[1]=new(cov_if_inst.rate_1);
.....
cg_rate_inst[15]=new(cov_if_inst.rate_15);

endfunction

endclass

It is working fine.But what is the Best approach to reduce the code
It is painful job to create 15 instances.
I just gave one example of Rate.There are so many signals like that i need to declare.
Any Expert Advice please.

Please help.

2

In reply to naaj_ila:

You can solve this issue by wrapping the covergroup into a class.

3

In reply to An Pham:

Hi Pham,

In that case i need to add 15 Covergroups, that will be again a BIG CODE.
Right?

4

In reply to naaj_ila:

Hi naaj_ila,

Sorry, I misunderstood the issue :)

The problem may be at the “ref” feature at covergroup. Why do you need “ref” at covergroup? Covergroups are just collectors, they shouldn’t change the sample values.

Just my guess, interface in SystemVerilog is a special type. In some cases it behaves like a module. Meanwhile, “ref” is a feature of class. So it depends on if the simulator supports this feature. I don’t know which simulator you are using, but it seems that the feature is not supported by your simulator.

– An –

5

In reply to An Pham:

Hi Pham ,

IO observed if i didnot give “ref” it is not sampling properly.
If we use a single instance , i think it will work without “ref”.
As i am usign multiple instances, it is not workign withour “ref”

I saw many satndard codes, they are using “ref”

6

In reply to naaj_ila:

Hi naaj_ila,

I dont understand why you get the problem if you remove “ref”. Nevertheless, if you want to keep it, there are two possible solutions for you:

  1. Change the simulator. Your simulator must be VCS.
  2. Write a script that generates the code for you. You can take a look at this link:
    system verilog - How to pass a variable value to a macro in SystemVerilog? - Stack Overflow

Btw, please correct your code. It has a lot of mistakes.

An,

7

In reply to An Pham:

Hi Pham ,
1.We cant change the simulator.
2.The code is just for reference. Thanks for suggestion

Can anybody else please help.

8

In reply to naaj_ila:

Hi Guys

I got the perfect answer .Check the link
http://www.verificationguild.com/modules.php?name=Forums&file=viewtopic&t=4882

Pham , u can know about the use of “ref” in that link

9

In reply to naaj_ila:

Hi naaj_ila,
I’ve just learnt a new thing.
Thanks :)