In reply to naaj_ila:
Hi naaj_ila,
Sorry, I misunderstood the issue :)
The problem may be at the “ref” feature at covergroup. Why do you need “ref” at covergroup? Covergroups are just collectors, they shouldn’t change the sample values.
Just my guess, interface in SystemVerilog is a special type. In some cases it behaves like a module. Meanwhile, “ref” is a feature of class. So it depends on if the simulator supports this feature. I don’t know which simulator you are using, but it seems that the feature is not supported by your simulator.
– An –