In reply to naaj_ila:
Hi naaj_ila,
I dont understand why you get the problem if you remove “ref”. Nevertheless, if you want to keep it, there are two possible solutions for you:
- Change the simulator. Your simulator must be VCS.
- Write a script that generates the code for you. You can take a look at this link:
system verilog - How to pass a variable value to a macro in SystemVerilog? - Stack Overflow
Btw, please correct your code. It has a lot of mistakes.
An,