Communication between sequence and scoreboard

UVM
,
1

Hello, I am implementing a scoreboard for the APB3 protocol and what can i do at scoreboard when only write transaction is done?, so as per my architecture for VIP. I am having a memory inside the slave sequence so that memory reacts as per the master transactions(Implemented reactive agent),so now i want to access that slave sequence memory inside the scoreboard for write transaction comparison so for comparison I want to read the slave sequence memory directly can you give any way how can i do that?

Thanks.

2

In reply to m_v:

Sending transactions from the sequence to the SB should not be used as a common approach. Any sequence generates seq_items which are visible in your UVM testbench when sent from the sequence to the target. You can observe this and send the transaction from there to the SB.

3

In reply to chr_sue:

hi chr_sue can you tell me what to do when in the testbench only write transaction is done but no read transaction is done then how you know that the master driver has driven the address and data correctly into the interface? In my case scoreboard is working only when write after read is done is this a good approach?

Thank you.

4

In reply to m_v:

Without seeing your testbench architecture it is not possible to give you a good advice. BTW the transaction should have an indication if it is read or write.

5

In reply to m_v:

“how do you know that the master driver has driven the address and data correctly into the interface?”

Those all sound like parts of your testbench. Are you trying to verify them, or the design? Are you modeling the memory with VIP? Most VIPs will have a backdoor API to read values. Don’t make yet another memory model in your sequence.

6

In reply to chr_sue:

This is my transaction class which has the enum for WRITE or READ transaction indication.

`ifndef APB_MASTER_TRANS_SV
`define APB_MASTER_TRANS_SV
  
class apb_master_trans extends uvm_sequence_item;
      
   //------------------------------------------
   // Data Members (Outputs rand)
   //------------------------------------------
   //Write Read transaction type enum handle
   rand trans_kind_e kind_e;
   randc bit [(`ADDR_WIDTH  - 1) :0] PADDR;
   rand bit [(`DATA_WIDTH  - 1) :0] PWDATA;
   rand bit [(`DATA_WIDTH  - 1) :0] PRDATA;
    
   constraint trans_type {soft kind_e == WRITE;}

   //UVM Factory Registration Macro
   //
     `uvm_object_utils_begin(apb_master_trans)
        `uvm_field_enum(trans_kind_e,kind_e,UVM_DEFAULT);
        `uvm_field_int(PADDR,UVM_DEFAULT | UVM_DEC);
        `uvm_field_int(PWDATA,UVM_DEFAULT | UVM_DEC);
    `uvm_object_utils_end

   //Constraint for the PADDR
   //
   constraint addr {soft PADDR inside {[0:30]};}

   //------------------------------------------
   // Methods
   //------------------------------------------

   //Standard UVM Methods:      
   function new(string name = "apb_master_trans");
      super.new(name);
   endfunction : new

endclass : apb_master_trans
`endif //APB_MASTER_TRANS_SV

and for the architecture please check this link:- APB-ARC-V7-v3 hosted at ImgBB — ImgBB

In this slave sequence have one memory that gives the read data whenever master send the read request.

Here my slave monitor samples the write transaction and read transaction both and put them into a analysis fifo which i have taken inside the slave sequencer and communication is done through analysis port and my slave sequence is retrieving that using get() method and when write transaction is there then write operation is done into memory of the slave sequence and when read transaction is there then read data is put into the transaction and using `uvm_send provided to the slave driver and slave driver drives the PRDATA to the interface.

Also my slave monitor monitors the PRDATA and provides it for comparison to scoreboard.

Thank you.

7

In reply to chrisspear:

Hello chrisspear, In my VIP if I want read data and there is no DUT then?, someone has to provide the read data, so what should i do?, can you help me with the right approach? and also can you tell me what this means “Most VIPs will have a backdoor API to read values”.

Thank you.

8

In reply to m_v:

What is your topology? I assume the testbench is generating AXI3 transactions. You said there is no DUT. Is the VIP acting as the DUT, a bus slave such as a memory?

You will need to read the documentation for your VIP. These often come with a library of examples, so find one that resembles what you are building. The documentation and example can show you how to check a read transaction. For example, the Siemens QVIP has the API function backdoor_read(address) that returns the data at that location.

9

In reply to chrisspear:

Hi, I am working on APB3 and and yes there is no DUT, and in VIP slave agent is providing the necessary control signals(PREADY) and read data(PRDATA) to the master, here I am trying to implement the Reactive agent, at master side I have master driver, master sequencer and master monitor, same for the slave agent there is slave driver, slave sequencer and slave monitor.

Master Agent:-
Master Driver:- Master driver drives the control signals(PSEL,PENABLE) and the PADDR and PWDATA with PWRITE signal for write or read transaction.

Master Monitor:- Master Monitor Monitors the PADDR, PWDATA and PWRITE signals and provides to the scoreboard.

Slave Agent:-
Slave Monitor:- Monitors the PADDR,PWDATA and PWRITE signals and provides it to the Slave sequencer via analysis port between slave monitor and the slave sequencer.

Slave Sequencer:- In sequencer I have taken one analysis fifo which stores the Write and Read transaction.

Slave Sequencer:- In this whole testbench at master side I have multiple sequences but for slave side I have only one sequence this sequence has one memory and this slave sequence gets the data form the analysis fifo of the slave sequencer and as per the transaction if write then writes into the memory and if there is read transaction then read from that memory, so when read transaction is there then this sequence puts the PWDATA into transaction class and provides it to the slave driver and slave driver drives it to to the interface.

Also for the scoreboard read data(PRDATA) is provided by the slave monitor through another analysis port between slave monitor and scoreboard.

This way I have implemented my VIP is this correct approach??

For the Architecture please check this link:- APB-ARC-V7-v3 hosted at ImgBB — ImgBB

Thank you…

10

In reply to m_v:

I’m trying to figure out what your testbench is trying to verify. All the testbench connections and interface BFM code? The diagram shows a DUT, but you said there was none.

Why do you have a memory in the sequence and another in the scoreboard? A memory seems like a component, not part of a string of dynamic transactions. If the sequence is really cool, someone may want to reuse it or start it twice. Would this create a second instance of the memory? Ouch! I would make the memory part of the slave agent, and share it with sequences and the scoreboard.

11

In reply to m_v:
as the monitor monitors first phase of information,sends it through analysis port to the sequencer. Then the sequence will be sent to the driver for execution. For Write or Read, its good please to put the memory model in the driver. Driver will drive the pready signal.
Monitor will monitor pready signal , capture the information , and send to scoreboard.

12

In reply to kddholak:

kddholak: I respectfully disagree. In an agent, the sequencer, monitor, and driver are components that receive a transaction, perhaps make a transformation between different representations such as UVM object and signal values, and send it to another part of the testbench. I don’t think they should hold long-term information about the contents of the design.

A VIP memory is tracking the expected state of the design. It is a new component in the agent. Sequences and scoreboards could access it via a handle in the agent configuration.

13

In reply to chrisspear:

Hello! chris spear sorry, I forgot to update the testbench architecture there was no DUT now i have updated it :- APB_VIP_ARCHITECTURE.png - Google Drive.

My Master Agent is verifying the Slave Agent functionality or visa versa ,and one another way is there currently, I am connecting my both master and slave agent but when i want to verify the slave DUT then i can make the slave agent of the VIP passive so that my DUT signals inside interface are not overlapped and it goes also for master DUT but now i don’t have any DUT, to verify master and slave are working as per the protocol for that i have connected them and taken a memory at the slave side. Also, can you tell me in general what VIP consists of?, and yes every time new instance will be created for slave sequence if you want to reuse it or start it twice, so now I will take memory inside the agent.

14

In reply to kddholak:

Hi, I also thought that we can take the memory inside the slave driver, monitor, sequencer or sequence, for this architecture i am taking it into the sequence now as per chris spear i need to take it inside the slave agent.