In reply to chrisspear:
Hi, I am working on APB3 and and yes there is no DUT, and in VIP slave agent is providing the necessary control signals(PREADY) and read data(PRDATA) to the master, here I am trying to implement the Reactive agent, at master side I have master driver, master sequencer and master monitor, same for the slave agent there is slave driver, slave sequencer and slave monitor.
Master Agent:-
Master Driver:- Master driver drives the control signals(PSEL,PENABLE) and the PADDR and PWDATA with PWRITE signal for write or read transaction.
Master Monitor:- Master Monitor Monitors the PADDR, PWDATA and PWRITE signals and provides to the scoreboard.
Slave Agent:-
Slave Monitor:- Monitors the PADDR,PWDATA and PWRITE signals and provides it to the Slave sequencer via analysis port between slave monitor and the slave sequencer.
Slave Sequencer:- In sequencer I have taken one analysis fifo which stores the Write and Read transaction.
Slave Sequencer:- In this whole testbench at master side I have multiple sequences but for slave side I have only one sequence this sequence has one memory and this slave sequence gets the data form the analysis fifo of the slave sequencer and as per the transaction if write then writes into the memory and if there is read transaction then read from that memory, so when read transaction is there then this sequence puts the PWDATA into transaction class and provides it to the slave driver and slave driver drives it to to the interface.
Also for the scoreboard read data(PRDATA) is provided by the slave monitor through another analysis port between slave monitor and scoreboard.
This way I have implemented my VIP is this correct approach??
For the Architecture please check this link:- APB-ARC-V7-v3 hosted at ImgBB — ImgBB
Thank you…