Communication between DUT and TB

SystemVerilog
1

Hi,
I’m not sure if this is the right place to ask this. Actually, I’m studying the book ‘SystemVerilog for Verification’ by Chris Spear. There is a paragraph explaining the usage of special functions for communication between DUT and TB which lacks examples. Can anyone help me understand how should such a function be written? Here’s the excerpt from the book:
“Lastly, it is a good practice for your testbench to use a function to get
information from the DUT. Reading signal values can work most of the time,
but if the design code changes, your testbench may interpret the values incorrectly.
A function in the module can encapsulate the communication between
the two and make it easier for your testbench to stay synchronized with the
design.”
Thanks in advance
Farhad

2

In reply to Farhad:
My guess is that a function can encapsulate a set of verification inquiries by poking into variables of several instantiated modules. This encapsulation brings more cohesiveness than putting all that code inline with the verification code. FOr example:


module m(
    input bit clk, a, 
    output bit b);
    bit x,w;
    // ...    
endmodule

module monitor(
    input bit clk, a, b);
    bit q, w;
    // ...    
endmodule


module top;
    timeunit 1ns;  timeprecision 100ps;    
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    bit clk, a, b, reset_n;
    m m1(.*);
    monitor mtr1(.*); 

    initial forever #10 clk = !clk; 
    function void do_check();
        if(m1.x==1'b1) am_xw: assert(mtr1.w==1'b1); 
        am_w: assert(m1.w==mtr1.q);
    endfunction 
  
     
    initial begin
      repeat (200) begin
        @(posedge clk);
         // ...
        do_check(); 
      $finish;
      end 
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

Thank you very much for your comprehensive answer. I got the point. Using the encapsulating functions prevents scattered access to module internals from all over the testbench, thus makes the code more organized and reduces the probability of making mistakes in case the module is modified.