Communication between DUT and TB

SystemVerilog
2

In reply to Farhad:
My guess is that a function can encapsulate a set of verification inquiries by poking into variables of several instantiated modules. This encapsulation brings more cohesiveness than putting all that code inline with the verification code. FOr example:


module m(
    input bit clk, a, 
    output bit b);
    bit x,w;
    // ...    
endmodule

module monitor(
    input bit clk, a, b);
    bit q, w;
    // ...    
endmodule


module top;
    timeunit 1ns;  timeprecision 100ps;    
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    bit clk, a, b, reset_n;
    m m1(.*);
    monitor mtr1(.*); 

    initial forever #10 clk = !clk; 
    function void do_check();
        if(m1.x==1'b1) am_xw: assert(mtr1.w==1'b1); 
        am_w: assert(m1.w==mtr1.q);
    endfunction 
  
     
    initial begin
      repeat (200) begin
        @(posedge clk);
         // ...
        do_check(); 
      $finish;
      end 
    end
  endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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