Clocking block in system verilog

SystemVerilog
1

Hi Experts,

I have a question on clocking blocks in system verilog.

I read some technical paper on simulation race conditions. The paper states the followings.

  1. The Sunburst Design Verilog testbench methodology typically assigned stimulus on the inactive
    clock edge (The clock edge which is not used by the DUT), typically far away from setup and hold times for the gate-level devices. This

  2. In system verilog, Synchronous testbenches can use the clocking block to avoid the race conditions.

My question is, can we write the clocking block without the interface module. I have an understanding that, the clocking block has to be always associated/tied/written with inteface.

Please help me to clarify.

Thanks,

2

In reply to chethan2807:

It can be declared in interfaces, modules and program blocks. As it mainly specifies the timing(sampling and driving time of signals[also known as input and output skew]) and synchronization of signals, mostly it is used with interfaces.

3

In reply to karan_18:

Hi Karan,

Thank you so much for the response. Let’s say we don’t have any interface modules in our design. In that case how where exactly we define the clocking block, inside the tb top?

4

In reply to chethan2807:

Simple example.


module tb();
  bit        clk;
  reg  [7:0] a;
  reg  [7:0] b;  
  wire [7:0] c;
  wire       d;
  
  default clocking cb @(posedge clk);
    default input #1 output #3;
    output  a,b;
    input c,d;
  endclocking
  
  initial begin
    clk=0;
    cb.a<=0;cb.b<=0;
    ##1 cb.a<=5;cb.b<=15;
    ##1 cb.a<=250;cb.b<=6;
    ##10;
    $finish;
  end
    
  always #5 clk = ~clk;
    
  dut o_dut(.clk(clk),.a(a),.b(b),.c(c),.d(d));
  
  initial begin
    $monitor("time: %0t => a:%0d,b:%0d,c:%0d,d:%0d",$time,a,b,c,d);
  end
endmodule

module dut(input wire clk,
           input wire [7:0] a,
           input wire [7:0] b,
           output logic [7:0] c,
           output logic d);
  
  always@(posedge clk) begin
    {d,c} <= a+b;
  end
endmodule