In reply to perumallatarun:
If there is a clock with frequency 1MHz and 30% duty cycle,how to check this clock if it has any glitches or not using System Verilog Assertions (SVA)?
The following solution works, and includes a testbench. That testbench follows the style demonstrated in my 4th edition SVA book regarding verifying assertions.
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk=1, a;
bit[0:1] t;
default clocking @(posedge clk); endclocking
initial forever begin
#298 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns clk=!clk;
end
else #2ns clk=!clk;
#398 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns;
end
else #2ns;
#300 clk=!clk;
end
property p_clk_hi;
time v;
@(posedge clk) (1, v=$time) |-> @(negedge clk) ($time-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
time v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($time-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115