Checker using SV Procedural code for request and ack

SystemVerilog
,
1

Hi,

I have a doubt in the implementation of the SV checker which checks if a valid request is asserted, there should be a grant after 10 clock cycles.

Code:
always @(posedge req)
begin
@(posedge clk);

fork: req_to_gnt
  begin: check_ack
    repeat (10) @(posedge clk); 
    @(posedge gnt)
    $display ("SUCCESS: Grant arrived in time ", $time);
    disable cntr;
  end:check_ack
  
  begin:cntr
    repeat(11) @(posedge clk);
    $display("ERROR:Grant did not arrive in time\n", $time);
    disable check_ack;
  end :cntr 
    
join_none

This code is not working for the input requests in two consecutive cycles.
Can someone help with implementing this checker without using SVA?

Thanks

2

In reply to ssakshi:
See my paper**- Understanding the SVA Engine,**
Verification Horizons - July 2020 | Verification Academy
It addresses in great details how to model SVA using the fork-join_none
The paper will answer your questions. The method you used is close, but you should sample the req and gnt with the clk. Also, make sure the tasks are automatic (they are if in a class).

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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3

In reply to ben@SystemVerilog.us:

Thanks!!