In reply to ssakshi:
See my paper**- Understanding the SVA Engine,**
Verification Horizons - July 2020 | Verification Academy
It addresses in great details how to model SVA using the fork-join_none
The paper will answer your questions. The method you used is close, but you should sample the req and gnt with the clk. Also, make sure the tasks are automatic (they are if in a class).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy - Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy