Cannot mix packed and unpacked types in this operation

SystemVerilog
, ,
1

I have the below code and the assignment is giving me “Cannot mix packed and unpacked types in this operation” as an error.
What options do I have to get this to work?


interface my_interface
  #(
     parameter int unsigned N
  )
  ( 
    outuput sig_o [N - 1 : 0]
  );

  bit     drv;
  logic   sig_i [N - 1 : 0];

  assign sig_o = drv ? sig_i : 1'hz;
endinterface
2

In reply to alessandro:

Use wire type in assign statement instead of reg.

Or the other way around is:

interface my_interface(outs);
 
  bit drv;
  logic   [3:0]sig_i;
  output [3:0]outs;
 
  assign outs = drv ? sig_i : 1'hz;
endinterface

Thanks.

3

In reply to sunils:

Having sig_i as a wire does not solve the issue unfortunately.

Thanks.

4

In reply to alessandro:

Use an array assignment pattern with a default. (section 10.9.1 in the 1800-2012 LRM)

assign sig_o = drv ? sig_i : '{default:'z};