Cannot mix packed and unpacked types in this operation

SystemVerilog
, ,
2

In reply to alessandro:

Use wire type in assign statement instead of reg.

Or the other way around is:

interface my_interface(outs);
 
  bit drv;
  logic   [3:0]sig_i;
  output [3:0]outs;
 
  assign outs = drv ? sig_i : 1'hz;
endinterface

Thanks.