Can we bind a checker to module inside other module?

SystemVerilog
, , ,
1 
checker cx1 (event e1, input logic i1,i2);
 ...
endchecker: cx1

module dut(input clk,i1, output reg i2);
 ...
endmodule: dut

module top();
logic clk = 0;
 logic i1, i2;
 initial forever #5 clk=!clk;
 ...
 bind dut cx1 bind_dut_checker(.i1(i1), .i2(i2), .e1(posedge clk));
endmodule: top
2

In reply to shubamg:

SystemVerilog provides a bind construct that is used to specify one or more instantiations of a module, interface, program, or checker without modifying the code of the target.

3

In reply to dave_59:

Thanks Dave!!