Can I use continuous assignment statement inside interface?

SystemVerilog
1

Hi,

I have to drive inout signal of DUT
so I have declared my interafce as below:

//interface
`timescale 1ns/1ps
interface tb_sys_interface;

timeunit 1ns;
timeprecision 100ps;
time clock_period = 30.3030ns;


wire x
logic x_reg ; // 
...........
...........
...........
initial
begin
x_reg = 0;
forever
begin
#(clock_period/2) x_reg = 1;
#(clock_period/2) x_reg = 0;
end
end
assign x=x_reg;
endinterface

when i run this in questasim x_reg VALUE is not getting assigned to x.so can you please tell me what is the issue with interface?
or this way of continuous assignment is allowed in interface?

2

In reply to SHARAT KOTTUR:

I ran your code and everything worked fine for me in QuestaSim. You will need to contact your vendor support team if you are encountering tool issues.

3

In reply to SHARAT KOTTUR:

Could you please mention the error you are getting.

Thanks,
Nikhil

4

In reply to SHARAT KOTTUR:

an interface is a module; your statement is allowed. you left a semi-colon off wire x?
besides that it looks ok.

5

I was attempting to use inout port inside interface with task in manipulating the inout signal.

But I can only get inout signal to update correctly, only if it’s included inside port list of the interface.

ioSig updates correctly when task is called:
Code:
interface my_if(inout wire ioSig)
assign ioSig = (sigEn == 1’b0) ? 1’b1 : 1’0;
…
task my_task;
…
begin
#10ns
sigEn = 1’b0;
…
ioSig fails to update:
Code:
interface my_if(…)
wire sigEn;
assign ioSig = (sigEn == 1’b0) ? 1’b1 : 1’0;
…
task my_task;
…
begin
#10ns
sigEn = 1’b0; // I’ve single step over here, no update on assign statement
…
What am I missing?

Thanks for any comments, PHP Training in Chennai | VMware Training in Chennai

6

Hi,

Here my issue is whatever iam driving on x_reg is not getting assigned to x.

when iam running im getting on signal x always as ‘x’.Iam using questasim 10.3d.Is that a tool issue?

7

In reply to SHARAT KOTTUR:

Am not sure of this but just initialize the x value to ‘0’ in the initial block, same as you have done to x_reg.

Thanks,
Nikhil

8

In reply to SHARAT KOTTUR:

If you are always seeing an ‘x’ on a signal, you will need to look at how that signal is being resolved. If you have an assign statement inside your interface, that is one driver of signal x. How is the signal x connected to the DUT? Is it connected to an output or inout? The DUT could be attempting to drive signal x as well, resulting in multiple drivers and an ‘x’ value.

9

Hi,

Thanks all for your suggestions.

In dut it is connected to an Inout signal.so whether instead of wire I have to drive it as Tri or trireg?

10

In reply to SHARAT KOTTUR:
See the bi-directional section of my DVCon paper The Missing Link: The Testbench to DUT Connection