Blocking Vs non-blocking assignment in for loop

SystemVerilog
, ,
1

Is the below two codes functionally same. what will be the synthesized structure ?

always_comb
begin
         for ( integer i = 0; i <= NUM; i = i + 1)
         begin
               c[i+1] <= a[i]  | b[i];

         end
end

always_comb
begin
         for ( integer i = 0; i <= NUM; i = i + 1)
         begin
               c[i+1] = a[i]  | b[i];

         end
end
2

In reply to svishnu:
The two examples you show are functionally the same, and there is no need for a for-loop. You could have written it as

logic [NUM+1:1] c;
logic [NUM:0] a,b;
always_comb c = a | b;

If you had the code

always_comb begin
    c <= a | b;
    d <= c + 1;
end

Now there is a significant difference in that second statement would be using the previous value of c, which no longer represents combinational logic and would be flagged as an error.

For this reason, you should never use non-blocking assignments in an always_comb block.

3

In reply to dave_59:

You’ll need for-loop if variables a, b, and c represented unpacked array.

4

In reply to dave_59:

I would like to know if the synthesized structure will be same for both code

5

In reply to svishnu:

Hey,

For your code, synthesized structure should be same for both the cases. But, as Dave explained you should not use non-blocking assignment to create combinational logic. And if you do, that might infer unintetional latch.