Blocking Vs non-blocking assignment in for loop

SystemVerilog
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2

In reply to svishnu:
The two examples you show are functionally the same, and there is no need for a for-loop. You could have written it as

logic [NUM+1:1] c;
logic [NUM:0] a,b;
always_comb c = a | b;

If you had the code

always_comb begin
    c <= a | b;
    d <= c + 1;
end

Now there is a significant difference in that second statement would be using the previous value of c, which no longer represents combinational logic and would be flagged as an error.

For this reason, you should never use non-blocking assignments in an always_comb block.