Automation of whole UVM Test bench

UVM
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1

Hi,

Is there any chance to automate the whole UVM test bench?
i.,e, we are able to generate the all components (interface, sequence item and so…on upto tb_top) wrt to provided RTL/DUT.
Could you please help me in giving an idea how to proceed further?
If we want to write a python script for the above thing, what are the things need to be consider

Thanks,
Furry_Panda

2

In reply to Furry_Panda:

If you mean the testbench generation, the answer is YES.
EDA companies are offering such tools as part of their license agreements.
But there are also framework generators on the market which are free-of-charge.
One you can find here
https://www.doulos.com/knowhow/systemverilog/uvm/easier-uvm/

3

In reply to chr_sue:

One such generation tool is available directly from the Verification Academy, the UVM Framework, with updates released every six months or so. A new version just dropped yesterday, 2023.1. All downloads and a useful array of video tutorials are available here:

https://verificationacademy.com/courses/UVM-Framework-One-Bite-at-a-Time