Asyncronous rst coding in SV

SystemVerilog
,
1

What is the best way to code a configurable asyncronous rst in SV ?
As it is a configurable rst it’s hard to use the posedge and negedge constructs.


c_act_rst <= 1'b0; // means i_rst is active LOW
c_act_rst <= 1'b1; // means i_rst is active HIGH

Is this the best way? :


    always_ff @(posedge i_clk or i_rst==c_act_rst)
        if (i_rst==c_act_rst)
            // signal rst behav
        else
            // signal clocked behav
    end

Thanx for the feedback you can provide!

2

In reply to stefaniecg:

i_rst is main reset signal?
c_act_rst is configurable reset signal (soft reset)?

Why don’t you use:


    wire rst_tmp = i_rst | c_act_rst; // assert at high level.
    always_ff @(posedge i_clk or posedge rst_tmp)
        if (rst_tmp)
            // signal rst behav
        else
            // signal clocked behav
    end

In design, we need to synchronize deasserted-reset signal to clock.

3

In reply to cuonghl:

Hey @cuonghl !
Thanx for your reply!

i_rst is the main reset signal (that is correct), but what I mean with c_act_rst is the polarity of the active reset, meaning:


c_act_rst <= 1'b0; // means reset is active LOW
c_act_rst <= 1'b1; // means reset is active HIGH

c_act_rst is a static parameter defined at compile time, i.e. is a constant.

4

In reply to stefaniecg:

You meant, c_act_rst is a constaint that decide which active level of i_rst (main rst)?

  • c_act_rst = 1’b0: then i_rst will active LOW
  • c_act_rst = 1’b1: then i_rst will active HIGH

If so, can you try:


   wire rst_tmp = (!c_act_rst) ? ~i_rst : i_rst;
    always_ff @(posedge i_clk or posedge rst_tmp)
        if (rst_tmp)
            // signal rst behav
        else
            // signal clocked behav
    end
5

In reply to cuonghl:

Thanx Chris (@cuonghl) !
I think that is a better way to code it :)