Asyncronous rst coding in SV

SystemVerilog
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4

In reply to stefaniecg:

You meant, c_act_rst is a constaint that decide which active level of i_rst (main rst)?

  • c_act_rst = 1’b0: then i_rst will active LOW
  • c_act_rst = 1’b1: then i_rst will active HIGH

If so, can you try:


   wire rst_tmp = (!c_act_rst) ? ~i_rst : i_rst;
    always_ff @(posedge i_clk or posedge rst_tmp)
        if (rst_tmp)
            // signal rst behav
        else
            // signal clocked behav
    end