Asyncronous rst coding in SV

SystemVerilog
,
2

In reply to stefaniecg:

i_rst is main reset signal?
c_act_rst is configurable reset signal (soft reset)?

Why don’t you use:


    wire rst_tmp = i_rst | c_act_rst; // assert at high level.
    always_ff @(posedge i_clk or posedge rst_tmp)
        if (rst_tmp)
            // signal rst behav
        else
            // signal clocked behav
    end

In design, we need to synchronize deasserted-reset signal to clock.