Asynchronous Stable Signal SVA

SystemVerilog
, , , ,
5

In reply to E_R_R:

Try:


// Code your testbench here
// or browse Examples
module tb();
 
    logic rst;
    logic o_sig;
 
    bit tmp_sig;
  
    initial begin
        rst = '1;
        #10;
        rst = '0;
      tmp_sig = 1;
        #20;
        rst = '1;
        #10;
        rst = '0;
      
      #100;
      tmp_sig = 0;
      #10;
 
      #100;
      $info ("Changing tmp_sig without RST");
      tmp_sig = 1;
      #10;
     #100;
      tmp_sig = 0;
      #10;

    end
 
    dut u_dut(   
        .rst(rst),
        .o_sig(o_sig)
    );
 
    a1 : assert property (
      @(tmp_sig) 1'b1 |-> $changed (rst));
 
 
endmodule : tb

It is not perfect - as the $changed(rst) is using tmp_sig as “clock” (to detect a change), so it sort of misses to flag the first change in tmp_sig without an accompanying change in rst, but guess you get the idea.