Asynchronous Stable Signal SVA

SystemVerilog
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4

In reply to E_R_R:
You could try something like the following:


/* The change of sig would be caused only by the change in the rst signal.
  Thus, in a perfect world they would happen simultaneously. 
  sig should only be able to change when rst does, but should be stable at all other times. */
// if(change in rst) then a change is sig is possible
// if(change in sig) && (no change in rst) then illegal

module m;
  bit sig, rst;
  bit sig_stretch, rst_stretch; // support

  always @(rst)  begin
    #1 rst_stretch =1;
    #1 rst_stretch =0; // need to tune this number. maybe #2 or #3
  end
  always @(sig)  begin
    #1 sig_stretch =1;
    #1 sig_stretch =0; 
  end
   
   am_sig: assert #0 (!(sig_stretch && !rst_stretch));  // no sig change when no rst
  
endmodule

Let me know if this is working for you or how you modified this.
Ben Cohen
Ben@systemverilog.us
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