I’ve got a situation in my SV code something along the lines of…
FRED_0_CH etc are single bit outputs.
assign FRED_0_CH = int_fred[0];
assign FRED_1_CH = int_fred[1];
assign FRED_2_CH = int_fred[2];
assign FRED_3_CH = int_fred[3];
…
…
etc
This is a very long list.
What I would like to do is put it in a loop but the the problem is how do I substitute the loop variable into assign FRED_0_CH etc?
Thanks,
Brian.
In reply to Witty:
HI,
Why do you want to depend on the Variable Name? You can take an array of that size like FRED_CH[10] and loop it over 10
In reply to Anudeep J:
Brian wants to assign DUT signals using loop, like following pseudo code which is not allowed:
foreach (int_fred[i])
assign $sformatf("FRED_%0d_CH",i) = int_fred[i];
AFAIK variable name formatting is not supported.
In reply to rohitk:
Ye rohitk, that is exactly what I want to do. Somebody has suggested to me that the answer MAY lie in using $sformatf. So that code fragment won’t work will it?
Thanks for the replies.
In reply to Witty:
The code Rohit shows will not work. The left hand side of the expression needs to be a static identifier at compile time. So the only sort of changes you can make would be with pre-processor compiler directives that get evaluated before compile. Unfortunately the SV pre-processor doesn’t have a looping mechanism
If the FRED_X_CH signals truly need to be their own independent signals as not an array themselves as Anudeep suggests, they will need to be written out separately
In reply to Witty:
Brian,
The code I showed is psuedo and won’t work in real, perl preprocessing can help you achieve what you are looking for. Take a look at following link :
Thanks,
Rohit
In reply to Witty:
The closest I could get to so far is below. It may be good to submit a for loop support in pre-processor to IEEE SV committee.
`default_nettype none
`define gen_bit_connect(sig_name, bit_num) \
assign sig_name``bit_num``_CH = int_fred[bit_num``];
module m;
logic FRED_0_CH, FRED_1_CH;
logic [3:0] int_fred;
`gen_bit_connect(FRED_, 0)
`gen_bit_connect(FRED_, 1)
// FRED_0_CH = int_fred[0];
initial begin : test
int_fred = '1;
#10;
$display ("FRED_0_CH: %b FRED_1_CH: %b", FRED_0_CH, FRED_1_CH);
end : test
endmodule : m
HTH
Srini
www.verifworks.com
In reply to Srini @ CVCblr.com:
In reply to Witty:
The closest I could get to so far is below. It may be good to submit a for loop support in pre-processor to IEEE SV committee.
`default_nettype none
`define gen_bit_connect(sig_name, bit_num) \
assign sig_name``bit_num``_CH = int_fred[bit_num``];
module m;
logic FRED_0_CH, FRED_1_CH;
logic [3:0] int_fred;
`gen_bit_connect(FRED_, 0)
`gen_bit_connect(FRED_, 1)
// FRED_0_CH = int_fred[0];
initial begin : test
int_fred = '1;
#10;
$display ("FRED_0_CH: %b FRED_1_CH: %b", FRED_0_CH, FRED_1_CH);
end : test
endmodule : m
HTH
Srini
www.verifworks.com
I tried to use a similar macro inside a generate statement, but since generate statements are processed at elaboration time (i.e after macro processing), the logic didn’t work. Is there a way to get the generate statement unrolled before macro processing or something on those lines?
In reply to sharat:
In reply to Srini @ CVCblr.com:
I tried to use a similar macro inside a generate statement, but since generate statements are processed at elaboration time (i.e after macro processing), the logic didn’t work. Is there a way to get the generate statement unrolled before macro processing or something on those lines?
Sharat,
That would require language extension like what I’ve suggested at the end of my previous post.
Srini
www.verifworks.com