Assigning single bits outputs in a loop

SystemVerilog
7

In reply to Witty:

The closest I could get to so far is below. It may be good to submit a for loop support in pre-processor to IEEE SV committee.

`default_nettype none
    
`define gen_bit_connect(sig_name, bit_num) \
    assign sig_name``bit_num``_CH = int_fred[bit_num``];

module m;
  logic FRED_0_CH, FRED_1_CH;
  logic [3:0] int_fred;
  
  `gen_bit_connect(FRED_, 0)
  `gen_bit_connect(FRED_, 1)
  // FRED_0_CH = int_fred[0];
  
  initial begin : test
    int_fred = '1;
    #10;
    $display ("FRED_0_CH: %b FRED_1_CH: %b", FRED_0_CH, FRED_1_CH);
  end : test
endmodule : m

HTH
Srini
www.verifworks.com