$assertoff giving error during compilation

SystemVerilog
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1

I used $assertoff() to disable assertions in my rtl. But its giving this error Only elaboration system tasks allowed here while compiling. How to resolve this issue?

2

In reply to vishnu_intel:

Can you show some part of code? Or some pseudo-code that gives the above error?

I guess that you are using $assertoff in wrong place. $assertoff must be used in some procedural blocks like initial/always blocks.

3

In reply to sharvil111:



module top;
  reg clk;
  reg [2:00]d;
  reg b ,c;

  initial begin
    clk=0;
d=0;
#5 d=1;
#2 d=2;
#4 d=3; 
#50 $finish;
  end
  always #4 clk=!clk;

**$assertoff();**
property d_stability;
@(posedge clk)
!$stable(d) |=> $stable(d) [*2];
endproperty : d_stability

assert property(d_stability);
endmodule
4

In reply to vishnu_intel:

As I mentioned, $assertoff needs to be in procedural block. Just add initial begin…end before $assertoff.

initial begin
$assertoff();
end