$assertoff giving error during compilation

SystemVerilog
, , ,
3

In reply to sharvil111:



module top;
  reg clk;
  reg [2:00]d;
  reg b ,c;

  initial begin
    clk=0;
d=0;
#5 d=1;
#2 d=2;
#4 d=3; 
#50 $finish;
  end
  always #4 clk=!clk;

**$assertoff();**
property d_stability;
@(posedge clk)
!$stable(d) |=> $stable(d) [*2];
endproperty : d_stability

assert property(d_stability);
endmodule