Hello ,
I am using signals named sop and eop for indicating the start of a packet and ending of a packet.
It should enable only for one clock cycle.If not error should occur.
How can i implement this error condition using concurrent assertion…
I am new to System verilog ang UVM…Please help me to get the answer.
what is antecedent and consequent in the assertion U intend to write…
I mean which signal you want to enable for one clock cycle?
In reply to Divyaa:
when Does sop signal becomes high. (Is it dependent on other signal?)
.Does sop signal work based on any other signal?
In reply to Ramchandra:
yes it depends on another signal called valid signal…
when valid is one sop should also be one…but only for one clock cycle…
then it should become 0.
Just look at this assertion, this checks for valid signal at every posedge of clock and also makes sure , sop comes to low/zero on second posedge of clock
property p1;
@(posedge clk)valid |-> ($rose(sop) ##1 $fell(sop));
endproperty:p1
assert property (p1);
In reply to Ramchandra:
if ur design requires sop must follow valid signal, then u must write another assertion to verify that sop doesn’t become true until valid signal is true
In reply to Ramchandra:
Thank you so much Ram…
Yes our design requires that sop should follow valid…
Could you please tell me how to implement that…
In reply to Divyaa:
property p2;
@(posedge clk) disable iff (rst)
(sop==0) until valid;
endproperty : p2
assert property(p2);
In reply to Divyaa:
I believe these assertions work fine. Its good to know how assertions work, sometimes intended result can’t be obtained unless we have a thorough knowledge about assertions and their working behaviour.
In reply to Ramchandra:
@ram In your answer, dont you think antecedent should be $rose(valid), since if valid is high for more clocks and sop comes for only a clock then your assertion will fail