Hello , I am using signals named sop and eop for indicating the start of a packet and ending of a packet. It should enable only for one clock cycle.If not error should occur. How can i implement this error condition using concurrent assertion… I am new to System verilog ang UVM…Please help me to…

Just look at this assertion, this checks for valid signal at every posedge of clock and also makes sure , sop comes to low/zero on second posedge of clock property p1; @(posedge clk)valid |-> ($rose(sop) ##1 $fell(sop)); endproperty:p1 assert property (p1);

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Divyaa January 24, 2015, 6:36am 3

In reply to Ramchandra:

sop signal…