I trying to write assertion to check that if valid is high, rsp should be high only after 8 clks. Valid can be high on consecutive clks and hence rsp should be high on consecutive clks as well.
**My question is if we were to implement the logic to drive rsp, we would use fork-join and call automatic task since this is pipelined process. Does assertion take care of this if it does how does that work? Is there a new assertion triggered every-time valid==1 and separate memory is allocated to check that assertion?
At E every clocking event (the @(posedge clk) the property of the assertion is triggered independently from any other triggered assertions and has a life of its own.
I posted on LinkedIn An anecdote: is SVA a soap pipe?
At every blow event of a soap pipe, a bubble property is emitted. That bubble has a life of its own. It begins to spin, examining its initial states and composition, and then has several outcomes:
· It could disappear as if this bubble property was totally meaningless and vacuous.
· It could split and issue a new property bubble, and this process can repeat itself multiple times. Each of these new bubbles then has a life of its own.
. One or more of these split bubbles could be seen shining with glow and happiness as if it succeeded, or it can come down in a flash crashing miserably into failure.
Note: I describe this analogy to SVA assertions as a response to questions I see at the https://verificationacademy.com/forums/systemverilog where many users fail to understand the SVA inner model on how properties are handles starting from the clocking event.
Actually, to better understand the SVA model, I encourage you to read my paper Understanding the SVA Engine,
In reply to UVM_SV_101:
Yes, an assertion takes care of this by creating a new thread for every attempt, each with its own set of local variables and state information.
Your property will not work because rsp is not necessarily 0 for the 8 cycle duration. You would have to do
property p1;
bit v;
@(posedge clk) (1,v=valid) ##8 rsp==v;
endproperty
After 8 cycles, there would be 8 threads, each with their own local copy of v.
Hi Dave,
According to logic there would be new thread every posedge of clk? Wouldnt that affect the performance?
Is there a way to put condition on it?
EDIT::
Oh never mind, that assertion takes care of valid==0, rsp==0 as well.
I have a question on the above assertion. I simulated it and i see the assertion passes at 170ns.I see the first detection of valid =1 happens at 30ns and then after 8 clock cycles inclusive, i dont see the rsp becoming one after 8 cycles and i still see the assertion passed. Can you help me tell why the assertion passed at 170ns?
In reply to rag123:
The assertion looks ok and it is a good solution.
The confusion may be in the way you read the waveforms.
// stimulus
@(posedge clk) #1;
if (!randomize(valid,rsp)
// valid is sampled in the Preponed region of @(posedge clk)
// From the waveform you when you see valid gong to a 1'b1, it is after 1 ns
// but regardless of that, the sampling of valid is zero not a one.
In reply to ben@SystemVerilog.us:
Ben, your assertion does not take care of the overlapping responses.
This solution has no overlapping issue. .
@(posedge clk) (valid==1) |-> ##8 rsp==1;
BTW this is identical to the the property with the “if” clause
Ben systemverilog.us