Assertion to check Synchronous de-assertion

SystemVerilog
,
2

In reply to Have_A_Doubt:
I am assuming that at the fell of rst_n the clk is running.
I am also assuming that by synchronous, you mean within acceptable bounds of a period.
IN this assertion, I save at the posedge of rst_n the current time.
I then wait till the next clock and measure the time difference to be within limits.


 module m;
   bit clk, rst_n;
   let period=10;
   property p;
     realtime v;
     @(posedge rst_n) (1, v=$realtime) ##0 
     @(posedge clk) ($realtime-v < period+1) && // <11
                    ($realtime-v > period-1);   // > 9 
   endproperty 
   ap_p: assert property(@(posedge clk) p); 
 endmodule
 // may need to adjust the units
     $realtime-v < period*1ns +0.1ns) && // <10.1ns
                ($realtime-v > period *1ns-0.1ns)
  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books:
  1. Papers:
    Understanding the SVA Engine,
    Verification Horizons
    Reflections on Users’ Experiences with SVA, part 1 and part 2
    Reflections on Users’ Experiences with SVA
    Reflections on Users’ Experiences with SVA - Part II
    SUPPORT LOGIC AND THE ALWAYS PROPERTY
    http://systemverilog.us/vf/support_logic_always.pdf
    SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
    SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
    SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
    https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.

====================

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Papers:
    Understanding the SVA Engine,
    Verification Horizons

Reflections on Users’ Experiences with SVA,

Reflections on Users’ Experiences with SVA, part 2

SUPPORT LOGIC AND THE ALWAYS PROPERTY

SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue

SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.

—---------------
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books:
  3. Papers:
    Understanding the SVA Engine,
    Verification Horizons
    Reflections on Users’ Experiences with SVA, part 1 and part 2
    Reflections on Users’ Experiences with SVA

SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/