In reply to ben@SystemVerilog.us:
I received an interesting new approach in resolving this assertion:
“I think that it be more efficient to use an always procedure that remembers that a bit has been set and then use an immediate assertion in a final block to check that all bits are set.” Below is code for that assertion. The complete model is at
http://SystemVerilog.us/bitset.sv
module top;
bit clk, go;
bit[3:0] fgs; // flags to check
bit[3:0] chkfgs;
default clocking @(posedge clk); endclocking
...
generate for (genvar g_i=0; g_i<4; g_i++)
always_ff @(posedge clk)
if(go && fgs[g_i]) chkfgs[g_i] <= 1'b1;
endgenerate
// ap_chkfgs: assert final (chkfgs==4'b1111); // Incorrect! see below
final ap_chkfgs: assert (chkfgs==4'b1111); // OK
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115