In reply to ben@SystemVerilog.us:
This works fine for me but problem is eventually property is not yet supported by all tools AFAIK. Is there any way we can achieve the same without using eventually.
generate for (genvar g_i=0; g_i<4; g_i++)
initial begin // opton2
wait(go);
ap_fgsbi: assert property( go |-> strong(fgs[g_i][-> 1]) );
end
endgenerate
Complete model is at http://SystemVerilog.us/bitset.sv
Results at end of sim
** Error: Assertion error.
Time: 930 ns Started: 50 ns Scope: top.ap_flags File: bitset.sv Line: 15
** Error: Assertion error.
Time: 930 ns Started: 50 ns Scope: top.genblk1[3].ap_fgsi File: bitset.sv Line: 21
** Error: Assertion error.
Time: 930 ns Started: 50 ns Scope: top.genblk2[3].ap_fgsbi File: bitset.sv Line: 28
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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