In reply to rohitk:
OOPS! There are TWO errors in my solution, and one in Srini’s
- My solution needs a strong sequence, as a weak sequence would not fail if not completed.
- This assertion needs to be fired ONCE. In both of our original solutions, at every clock yo have a new attempt, and some of those later attempts could produce a failure.
Below is a solution that will work for you. I am assuming that during the first 45 time units, the system is being initialized, and after that, you have a go signal. You don’t need this go signal if you want the assertion to be fired once at time 0.
// assertion to check if all bits get set atleast once in simulation for a multibit vector
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, go;
bit[3:0] fgs; // flags to check
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
property p_flags;
bit[3:0] v=0;
go |-> strong( (1, v=v | fgs)[*1:$] ##0 (v==4'b1111));
endproperty
initial begin // option 1
wait(go);
ap_flags: assert property(p_flags);
end
generate for (genvar g_i=0; g_i<4; g_i++)
initial begin // opton2
wait(go);
ap_fgsi: assert property( go |-> s_eventually fgs[g_i]);;
end
endgenerate
initial begin
#45 go <= 1'b1;
repeat(25) begin
@(posedge clk);
if (!randomize(fgs) with
{$countones(fgs)==1;
fgs <= 7;
}
) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115