Assertion to check if all bits get set atleast once in simulation for a multibit vector

SystemVerilog
,
5

In reply to Srini @ CVCblr.com:

Hi Srini,

Thanks for helping, your solution works fine but it always fails in the end if bits gets set to 0. I had to modify it a bit to get it working for my case:

property p_check_single_bit_to_be_set;
enb |-> s_eventually fgs[0];
endproperty : p_check_single_bit_to_be_set

a_p_check_single_bit_to_be_set : assert property (p_check_single_bit_to_be_set)
enb=0;
else
$display(“SVA”, “Bit was never set to 1”);

I incorporated this change from Ben’s solution.

This works fine for me but problem is eventually property is not yet supported by all tools AFAIK. Is there any way we can achieve the same without using eventually.

Thanks again for helping me out.

Regards,
Rohit