Assertion to check if all bits get set atleast once in simulation for a multibit vector

SystemVerilog
,
3

In reply to rohitk:

How about?


  // Assuming default clock & disable

  property p_check_single_bit_to_be_set;
    s_eventually p_flags[0];
  endproperty : p_check_single_bit_to_be_set

  a_p_check_single_bit_to_be_set : assert property (p_check_single_bit_to_be_set) else
    `uvm_error ("SVA", "Bit was never set to 1")

Combine that with a generate loop for scalable bits

Regards
Srini
http://www.verifworks.com