In reply to rohitk:
// assertion to check if all bits get set atleast once in simulation for a multibit vector
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, enb=1;
bit[3:0] fgs; // flags to check
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
property p_flags;
bit[3:0] v=0;
enb |-> (1, v=v | fgs)[*1:$] ##0 (v==4'b1111 || enb==0);
// When enb gets set to 0, another attempt gets started in the Preponed region
endproperty
ap: assert property(p_flags) enb=0;
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(fgs) with
{$countones(fgs)==1;}
) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115