Assertion to check clock toggling

SystemVerilog
,
2

In reply to TRUSHAL:
If you rephrase your requirements, the assertion is trivial.
I read the requirements as : If a==1 there can be toggling


module m;
  bit a, clk;
  int err; 
  initial forever #5 clk = !clk;
  ap_1: assert property (@(clk) strong (a)) else err=err+1;

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    repeat (6) @(posedge clk) randomize(a);
    #100;
    $finish;
  end
endmodule
 of clk. 
        
  ap_clk:  assert property(@(clk) a)
                 count=count+1; // count is for debug

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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