Assertion to check a signal asserting before or after few clock cycles

[PavanSP]

I have a signal ‘b’ which should be asserted before say 10 cycles OR after 10 cycles of another signal ‘a’ being asserted.
$rose(a) |-> ##[-10:10] $rose(b) //which is syntactically wrong

I tried implementing this way:

		property rise_a;
			$rose(a) |-> ##[0:10] (b);
		endproperty: rise_a
		property rise_b;
			$rose(b) |-> ##[0:10] (a);
		endproperty: rise_b
		property combine_event; @(posedge clk) 
			rise_a or rise_b;
		endproperty: combine_event

	assert_event:
		assert property(combine_event)
			else `uvm_error("ASSERT", "error")

This takes account of rise of signal b too which I want to ignore.
Please suggest me a better way to do this.

[ben2]

In reply to PavanSP:
Consider the following with a lock variable to lockout the rose(a) or rose(b) if one was triggered.

    bit clk, a, b, lock;  
    initial forever #10 clk=!clk;  
    
    function void setlock(bit x);
      lock=x;
    endfunction

    ap_a: assert property(@ (posedge clk) 
         ($rose(a) && !lock, setlock(1)) |-> ##[0:10] (b) ##0 (1, setlock(0))) 
              else setlock(0);  // releas lock if pass or fail 

    ap_b: assert property(@ (posedge clk)  
         ($rose(b) && !lock, setlock(1)) |-> ##[0:10] (a) ##0 (1, setlock(0)))
              else setlock(0);  

 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

---

1. SVA Alternative for Complex Assertions
   Verification Horizons - March 2018 Issue | Verification Academy
2. SVA: Package for dynamic and range delays and repeats | Verification Academy
3. SVA in a UVM Class-based Environment
   SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy

[ben2]

In reply to ben@SystemVerilog.us:
You may want to consider 2 sets of locks to handle boundary conditions

bit clk, a, b, locka, lockb;  
    initial forever #10 clk=!clk;  
 
    function void setlocka(bit x);
      locka=x;
    endfunction
    function void setlockb(bit x);
      lockb=x;
    endfunction
 
    ap_a: assert property(@ (posedge clk) 
         ($rose(a) && !lockb, setlockb(1)) |-> ##[0:10] (b) ##0 (1, setlockb(0))) 
              else setlockb(0);  // release lock if pass or fail 
 
    ap_b: assert property(@ (posedge clk)  
         ($rose(b) && !lock, setlocka(1)) |-> ##[0:10] (a) ##0 (1, setlocka(0)))
              else setlocka(0);   

I did not test this, but these are things you can consider and verify.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

---

1. SVA Alternative for Complex Assertions
   Verification Horizons - March 2018 Issue | Verification Academy
2. SVA: Package for dynamic and range delays and repeats | Verification Academy
3. SVA in a UVM Class-based Environment
   SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy