In reply to PavanSP:
Consider the following with a lock variable to lockout the rose(a) or rose(b) if one was triggered.
bit clk, a, b, lock;
initial forever #10 clk=!clk;
function void setlock(bit x);
lock=x;
endfunction
ap_a: assert property(@ (posedge clk)
($rose(a) && !lock, setlock(1)) |-> ##[0:10] (b) ##0 (1, setlock(0)))
else setlock(0); // releas lock if pass or fail
ap_b: assert property(@ (posedge clk)
($rose(b) && !lock, setlock(1)) |-> ##[0:10] (a) ##0 (1, setlock(0)))
else setlock(0);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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